Xilinx Field Programmable Gate Array, Part #: XC7K325T-2FBG676I | FPGA | DEX A9B10017152 The device is designed to

The device is designed to work with a 1 F input and a 1 F output ceramic capacitor

Other features include soft start mode to reduce inrush current during start up

DKx#) and output data clocks (QKx

Part #LM2586SX-ADJ | Regulator | DEX features: • Requires Few External Components • Family of Standard Inductors and Transformers • NPN Output Switches 3 A

4-way set-associative data cache with ECC (independent for each CPU) o 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs) Dual-core Arm Cortex-R5F Based Real-Time Processing Unit (RPU)  CPU frequency: Up to 600MHz  Armv7-R Architecture o A32/T32 instruction set  Single/double precision Floating Point Unit (FPU)  CoreSight™ and Embedded Trace Macrocell (ETM)  Lock-step or independent operation  Timer and Interrupts: o One watchdog timer o Two triple-timer counters  Caches and Tightly Coupled Memories (TCMs) o 32KB Level 1

Xilinx Field Programmable Gate Array, Part #: XC7K325T-2FBG676I | FPGA | DEX A9B10017152 The device is designed toXilinx Field Programmable Gate Array, Part #: XC7K325T 2FBG676I is built on a state of the art, high performance, low power (HPL), 28 nm, high k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2. 9 Tb s of I O bandwidth, 2 million logic cell capacity, and 5. 3 TMAC s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and