Xilinx Field Programmable Gate Array, Part #: XC7Z007S-2CLG225I | FPGA | DEX all-chips QKx#) • On-die DLL generates

QKx#) • On-die DLL generates CK edge-aligned data and differential output data clock signals • 64ms refresh (128K refresh per 64ms) • 168-ball BGA package • Ω or 60Ω matched impedance outputs • Integrated on-die termination (ODT) • Single or multibank writes • Extended operating range (200–1200 MHz) • READ training register • Multiplexed and non-multiplexed addressing capabilities • Mirror function • Output driver and ODT calibration • JTAG interface (IEEE 1149

MRC:P58-00061

Superior strength with better puncture resistance

six linear regulators

2K/4K/4K bytes SRAM

Xilinx Field Programmable Gate Array, Part #: XC7Z007S-2CLG225I | FPGA | DEX all-chips QKx#) • On-die DLL generatesXilinx Field Programmable Gate Array, Part #: XC7Z007S 2CLG225I is built on a state of the art, high performance, low power (HPL), 28 nm, high k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2. 9 Tb s of I O bandwidth, 2 million logic cell capacity, and 5. 3 TMAC s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and