QAAUTO TEST PART Nividia The bipolar/MOS combination provides an

The bipolar/MOS combination provides an extremely low-power latch with maximum interface flexibility

and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • TC of 95°C – 64ms

and connectivity capabilities

Flexible external memory controller with up to 32-bit data bus: SRAM

Xilinx Field Programmable Gate Array Part #XC7VX550T-1FFG1927C

QAAUTO TEST PART Nividia The bipolar/MOS combination provides anQAAUTO TEST PART