Xilinx Field Programmable Gate Array - FPGA - part # XC5VLX30-1FF676C GE IGBT Line Side 1.5 GEN1 ESS 5 ns instruction cycle at

5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)– One-cycle 32-bit addition and subtraction with 40-bit result– One-cycle multiplication (16 × 16 bit)– Background division (32 / 16 bit) in 21 cycles– One-cycle multiply-and-accumulate (MAC) instructions– Enhanced Boolean bit manipulation facilities– Zero-cycle jump execution– Additional instructions to support HLL and operating systems– Register-based design with multiple variable register banks– Fast context switching support with two additional local register banks– 16 Mbytes total linear address space for code and data– 1024 Bytes on-chip special function register area (C166 Family compatible)– Integrated Memory Protection Unit (MPU)

RACK-MOUNTED EATON EVLL1150R-1U

5115140-11

Gamesa Part# GP011681

Two differential clock inputs WCK_t/WCK_c per channel for data (DQ

Xilinx Field Programmable Gate Array - FPGA - part # XC5VLX30-1FF676C GE IGBT Line Side 1.5 GEN1 ESS 5 ns instruction cycle atThe Spartan 3 family of FPGA's is specifically designed to meet the needs of high volume, cost sensitive consumer electronic applications. The eight member family offers densities ranging from 50,000 to 5,000,000 system gates. Features Low cost, high performance logic solution for high volume, consumer oriented applications Densities up to 74,880 logic cells SelectIO interface signaling Up to 633 I O pins 622+ Mb s data transfer rate per I O 18 single